Silicon on Insulator (SOI) devices are very attractive for high performance VLSI. Thin film SOI devices have advantages such as improved short channel effects and subthreshold slope, higher mobility, freedom from latch-up, reduced parasitic capacitances and reduced power. In the past, fabrication of radiation-hardened devices was the first commercial application of SOI. This use developed from work aimed at replacing expensive silicon on sapphire for military radiation-hardened devices. The most advanced commercial product in this arena now is SRAM (256 Kb). Up to now, however, use of SOI for the fabrication of DRAM has not been believed to be practical.
One drawback of the SOI DRAM is the high cost of SOI wafers. In addition, fabricating an SOI DRAM cell is significantly complex compared to conventional DRAM cells. It is very difficult to etch trenches in conventional SOI substrates because trenches are normally etched using oxide masks. As a result, DRAM cells on SOI substrates use stacked capacitors placed above the oxide insulator of the SOI substrate. Stacked capacitors inherently have low storage capacitance, and introduce planarization problems. Further, the prior art SOI DRAM cells, which include stacked capacitor storage nodes, suffer from such drawbacks as parasitic sidewall leakage, high soft error rates, and well-to-substrate leakage.